The density of the memories being fabricated is rapidly increasing and at a fast pace compared to random logic. Additionally, the percentage of embedded memories in a chip is increasing, thereby occupying a major portion of a system-on-a-chip. The smaller feature size and increasing real estate occupied by memories on a chip result in an enormous critical chip area that may potentially have defects. The traditional use of Direct Memory Access (DMA) for testing is costly in terms of silicon area, routing complexity, and test application time. BIST (built-in-self-test) has become an attractive alternative and can offer benefits such as high fault coverage. Traditionally, given the type of memories and the tests that need to be applied to them, memories have been grouped and assigned to particular controllers. For example, a SOC (System on a Chip) with roughly 200 memories is usually grouped and assigned to 25-30 controllers, where each controller is responsible for managing the tests of between 4-10 memories. The controllers are designed in a way such that they are capable of running the exact pre-established algorithms in a pre-specified sequence during manufacturing test. Since such controllers are non-programmable (or hard-wired), the algorithms and the fault models they target are fixed and cannot be changed at a later time after the chip has been manufactured.